1. Introduction and Overview. - 1. 1 Device vs System Scaling. - 1. 2 Major Implementation Issues. - 1. 3 ESPRIT 824 WSI Program. - References. - 2. Interconnect Issues. - 2. 1 Physical Interconnect Hierarchy. - 2. 2 Recursive vs Non-Recursive Interconnect Links. - 2. 3 On-Chip Interconnect Lengths. - 2. 4 Inter-Chip Connection Lengths. - 2. 5 Electrical Models of Interconnection Lines. - 2. 6 Minimum Line Capacitance. - 2. 7 Scaling of On-Chip Interconnections. - 2. 8 Chip-to-Board Interconnect Discontinuity. - 2. 9 Comparison of Packaging Schemes. - 2. 10 Clock Distribution and Clock Skew. - References. - 3. Fabrication Defects. - 3. 1 Substrate defects. - 3. 2 Lithography-induced defects. - 3. 3 Thin Film Defects. - References. - 4. Reliability and Failures. - 4. 1 Failure rate modeling. - 4. 2 General reliability of IC's. - 4. 3 Failure due to metal electromigration. - 4. 4 Failure rates under MOS dimensional and voltage scaling laws. - References. - 5. Yield models and Analysis. - 5. 1 General yield models. - 5. 2 Early yield models. - 5. 3 General IC yield models. - 5. 4 VLSI yield models based on yield observations. - 5. 5 Defect size distributions and critical areas. - 5. 6 Yield simultion in VLSI CAD tools. - 5. 7 Appendix. - References. - 6. Fault Modeling. - 6. 1 General fault modeling issues. - 6. 2 Definitions. - 6. 3 Stuck-at faults and weak 0/1 faults. - 6. 4 Stuck transistor faults. - 6. 5 Bridging faults. - 6. 6 Metastability in latches and flip-flops. - References. - 7. General testing techniques. - 7. 1 General Test issues. - 7. 2 Scan path test design. - 7. 3 LSSD-based Test Methodologies. - 7. 4 Pseudorandom test pattern generators. - 7. 5 Test response compression. - References. - 8. Function-Specific Testing. - 8. 1 Memory testing. - 8. 2 Built-in testing of regular arrays. - 8. 3 Testable programmable logic arrays. - References. - 9. Physical Restructuring. - 9. 1 General Restructuring Techniques. - 9. 2 Laser zapping for memory repair. - 9. 3 Electronically field-programmable anti-fuses. - 9. 4 Laser-assisted chemical processing. - 9. 5 Focussed ion beams for restructuring. - 9. 6 Electron beam restructuring. - 9. 7 Restructurable VLSI program. - References. - 10. Programmable Electronic Reconfiguration Switches. - 10. 1 General switching issues. - 10. 2 Reconfigurable processors. - 10. 3 WASP (The WAfer-scale Systolic Processor). - 10. 4 Representative switch configurations. - 10. 5 Non-lattice reconfiguration switch organizations. - References. - 11. Formal Models of Reconfiguration. - 11. 1 Introduction. - 11. 2 Probabilistic bounds: Linear arrays. - 11. 3 Probabilistic bounds: 2-dimensional arrays. - 11. 4 The Diogenes approach of Rosenberg. - 11. 5 Self-reconfiguration algorithms. - 11. 6 Spare roow/column allocation algorithms. - References. - 12. Silicon Wafer Hybrids. - 12. 1 Introduction. - 12. 2 Wafer transmission module. - 12. 3 AVP modules. - 12. 4 Programmable hybrid wafer circuits. - 12. 5 MicroChannel cooling and chip attachment. - 12. 6 Microwave performance issues. - 12. 7 Chip Templates. - 12. 8 Other Silicon Circuit Board Studies. - References. - 13. Optical Interconnections. - 13. 1 optical interconnects. - 13. 2 Optical Interconnect Components. - References. Language: English